1. Field of the Invention
A semiconductor device and a microelectromechanical system package and a method of making the same involve vertically packaging and simultaneously electrically interconnecting a plurality of semiconductor chip scale substrates using high performance vias.
2. Discussion of the Related Art
Prior vertical packaging techniques require forming an integrated circuit (IC) stack with epoxy followed by mechanically lapping the sides of this formation in preparation for forming the interconnect between the IC's in the stack along these sides of the stack. Prior techniques require the formation and attachment of lead frames to each die in order to bring what would have been bonding pads out to the edges of the stack. Some prior techniques employ conductive epoxy for signal and power traces along the sides of the stack. This technique, which is particularly hand labor intensive is expensive.
Prior vertical packaging techniques have largely eluded or otherwise resisted assembly automation and any incorporation into the regular wafer fabrication context. Thus, products of these prior techniques have been very expensive, and quality/consistency challenged and, in the case of memory chips, frequently overtaken in capacity by the next generation chips. New personal electronic appliances require evermore memory in order to enable the greater array of functionality that consumers demand. Some examples of these are cell phones, cameras and personal digital assistants and new, future appliances that contain the convergence of these. And now, the packing density of memory chips will reach its limit known in the art where devices can be made so small that they no longer exhibit useful behavior.